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TA1270BFG
TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA1270BFG
PAL / NTSC VIDEO CHROMA AND SYNC PROCESSING SYSTEM FOR PIP / POP / PAP
TA1270BFG is a PAL / NTSC color TV signal processor IC suitable for PIP / POP / PAP. The IC integrates video, chroma and sync processor circuits. It comes in a 48pin flat package. The video block uses a chroma trap, the chroma block a PAL / NTSC automatic identifier circuit, and the sync processor block a 50 / 60 Hz automatic identifier circuit. The PAL demodulator circuit contains a baseband signal processor, making the circuit adjustment free. The TA1270BFG incorporates an I2C bus, enabling control to be set via the bus line.
FEATURES
Video block
Chroma trap Y delay line Sub contrast adjustment (3 dB) Weight: 0.83 g (Typ.)
CHROMA block
UV / CbCr demodulation for NTSC ; UV demodulation for PAL Tint control PAL demodulation baseband signal processing PAL / NTSC automatic identification Sub color adjustment (3 dB)
Sync processor block
High-performance sync separator circuit Adjustment-free horizontal and vertical oscillator circuit using count down method 50 / 60 Hz automatic identifier circuit
Switch block
High-speed switcher circuit YUV or RGB input Built-in RGB matrix circuit YUV or RGB output
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BLOCK DIAGRAM
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PIN FUNCTION
PIN No. PIN NAME FUNCTION INTERFACE INPUT / OUTPUT SIGNAL
1 2 3
X'tal-1 X'tal-2 X'tal-3
Connect crystal. Serial capacitance can vary oscillator frequency f0 ; parallel capacitance can vary oscillator adjustment range.
DC 4.0 V 90 mVp-p
4
APC filter
Connect APC filter for CHROMA demodulation. The voltage of this pin determines the VCXO oscillator frequency.
DC
5
C GND
CHROMA processor GND pin
6
CHROMA input
CHROMA input pin. Input CHROMA signal after Y / C separation.
1.8 V
7
V-SEP
Connect vertical sync separation filter.
DC 6.4 V
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PIN No. PIN NAME FUNCTION INTERFACE INPUT / OUTPUT SIGNAL
8
Sync input
Sync separator circuit input pin. Input via the clamp capacitor.
2.5 V
9
Sync output
Outputs sync signal separated using the sync separator circuit. Open collector output. Connect a pull-up resistor.
10
AFC filter
Connect a horizontal AFC filter. The voltage of this pin determines the horizontal output frequency.
DC
11
SYNC GND
Sync processor GND pin
12
32 fH VCO
Connect a ceramic oscillator for horizontal oscillation. Use a CSBLA503KECZF30 oscillator manufactured by Murata Mfg Co., Ltd.
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PIN No. PIN NAME FUNCTION INTERFACE INPUT / OUTPUT SIGNAL
13
VP output
Vertical pulse output pin
14
HD output
Outputs HD pulse processed by the AFC. HD output phase or pulse width can be changed by bus setting.
15
SCP output
Outputs sand castle pulse (SCP). The output signals are clamp pulse, horizontal blanking pulse, and vertical blanking pulse. The minimum load resistance is 3 k.
7.9 V 4.3 V 2.5 V
16
Dig GND
Logic block GND pin
17
CP / HP input
Input pin for CP / HP pulse used to operate the SW circuit. CP is used as clamp pulse ; HP as blanking pulse.
18 19
SYNC VCC SW VCC
VCC pins for sync processor block and SW block. Connect 9 V (Typ.).
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PIN No. PIN NAME FUNCTION INTERFACE INPUT / OUTPUT SIGNAL
20 21 22
Y / G output B-Y / B output R-Y / R output
Output Y / B-Y / R-Y or R / G / B. YUV / RGB output is switched by bus setting.
Pin used to switch slave addresses. 23 ADRS SW GND VCC 24H, 2CH
2CH 0.7 V 24H GND
24
SW GND
Switch block GND pin
25 26 27
Y2 input B-Y2 input R-Y2 input (YUV2)
Y2 / B-Y2 / R-Y2 (YUV2 input) or R2 / G2 / B2 input pin. Input via capacitor used for clamp operation.
28 29 30 31
I C GND Y1 input B-Y1 input R-Y1 input (YUV1)
2
I C block GND pin Y1 / B-Y1 / R-Y1 (YUV1 input) or R1 / G1 / B1 input pin. Input via capacitor used for clamp operation.
2
Same as those for pins 25, 26 and 27
32
Ys
High-speed switch for switching input pins 25, 26, and 27 (YUV2) and input pins 29, 30, and 31 (YUV1). The threshold is 0.7 V.
YUV1 0.7 V YUV2 GND
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PIN No. PIN NAME FUNCTION INTERFACE INPUT / OUTPUT SIGNAL
33
SCL
I C Bus SCL pin
2
34
SDA
I C Bus SDA pin
2
35
DAC TEST
DAC monitor pin for IC shipping inspection.
36
GND
GND pin
37
Y output
Outputs Y signal which passed fsc trap (trap is set on or off by Bus) and Y delay line circuit.
38 39
DAC2 DAC1
1 bit DAC output pins
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PIN No. PIN NAME FUNCTION INTERFACE INPUT / OUTPUT SIGNAL
40
Y input
Composite video signal or Y signal input pin. Input via the clamp capacitor.
2.4 V
41 42
DAC VCC C VCC
VCC pins for DAC block and CHROMA processing block. Connect 5 V (Typ.).
43
UV / CbCr SW
UV / CbCr demodulation switch. OPEN UV GND CbCr CbCr demodulation is effective for NTSC only.
UV 0.7 V CbCr 0
44
fsc output
Outputs crystal oscillator fsc. The pin voltage goes high only when 3.58NTSC is received.
AC ; 0.6 Vp-p DC ; 3.58NTSC 3.2 V OTHERS 1.6 V
45
1HDL CONT
Outputs PAL / SECAM / NTSC identification result. Adjust to DC and connect output to 1H DL IC.
4.3 V ; PAL 2.5 V ; SECAM 0 V ; NTSC
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PIN No. PIN NAME FUNCTION INTERFACE INPUT / OUTPUT SIGNAL
46
SECAM CONT
I / O pin used to control SECAM demodulator IC. If 250 A or more flows from this pin, SECAM is determined.
At PAL / NTSC : 3.7 V
At SECAM (Black and white) : 0.7 V
47
B-Y / Cb output
Outputs B-Y (U) signal or Cb signal. Incorporates LPF to reject carrier.
Pedestal level: 2.4 V
48
R-Y / Cr output
Outputs R-Y (V) signal or Cr signal. Incorporates LPF to reject carrier. Pulling up the pin with 10 k monitors CHROMA signal after ACC and TOF circuits (before demo input).
R-Y output Pedestal level: 2.7 V Cr output Pedestal level: 2.5 V
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BUS CONTROL MAP
Write data Slave address : 24H (00100100) pin 23-GND or 2CH (00101100) pin 23-VCC
SUB ADDRESS 00 01 02 03 04 05 06 TOF-f0 SUB CONTRAST SUB COLOR Y BLACK LEVEL ADJ. R-Y BLACK LEVEL ADJ. B-Y BLACK LEVEL ADJ. SW-OFT D7 MSB D6 D5 D4 TINT TOF-Q C-TRAP Y-DL HD-PHS D3 D2 D1 D0 LSB DAC1 P / N-ID DAC2 POWER-ON INITIAL VALUE MSB LSB 1000 1000 1000 1000 1000 1000 1000 0000 0000 0000 0000 0000 0000 0000
COLOR SYSTEM V-FREQ / AFC-G GP-PHS Y-OFST
OUTPUT MODE
Read data Slave address : 25H (00100101) pin 23-GND or 2DH (00101101) pin 23-VCC
D7 0 1 PORET 1 D6 D5 D4 X'tal X'tal D3 D2 V-FREQ N-DET D1 V-STD U2 / V2-IN D0 H-LOCK Y2-IN
COLOR SYSTEM COLOR SYSTEM
BUS CONTROL FUNCTION
Write function
PARAMETER TINT DAC1 / 2 TOF-f0 TOF-Q Y-DL P / N ID SUB CONTRAST C-TRAP HD-PHS SUB COLOR Adjusts hue. -32~+32 Controls 1 bit DAC. 0 : LOW, 1 : HIGH Switches TOF peak frequency. (000) : TOF OFF, (001) : 0.8 fsc, (111) : 1.5 fsc Switches TOF Q ; (000) : 0.6~(111) : 1.2 Switches Y-DL delay time ; (0) : OFF, (1) : ON (+80 ns) Switches PAL / NTSC identification sensitivity. (0) : LOW (Digital comb filter in use), (1) : Normal Adjusts sub contrast ; -3.0 dB~+3.0 dB Switches CHROMA trap ; (0) : OFF, (1) : ON Switches HD output pulse phase ; (0) : PHASE-1, (1) : PHASE-2 (SCP) Sub color ; -5.3 dB~0 dB~+3.0 dB Switches color system. (000) : AUTO COLOR SYSTEM (011) : PAL (101) : N-PAL Y BLACK LEVEL ADJ. SW-OFT (001) : 3NTSC (100) : M-PAL (110) : SECAM (010) : 4NTSC (101) : N-PAL (111) : TRINORMA (1000) OFF (000) AUTO DESCRIPTION POWER-ON INITIAL VALUE 0 LOW (100) CENTER MIN OFF LOW 0dB OFF PHASE-1 0dB
Adjusts Y black level ; -75 mV~+65 mV Switches SW output offset ; Y : -10 IRE & UV : +60 mV ON / OFF (0) : OFF, (1) : ON
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PARAMETER DESCRIPTION Controls vertical frequency and horizontal free run. V FREQUENCY (000) (001) V-FREQ / AFC-G (010) (011) (100) (101) (110) (111) B-Y / R-Y BLACK LEVEL ADJ. GP-PHS Y-OFST AUTO1 (50 / 60 Hz MODE) 60 Hz MODE 262.5H forced 312.5H forced AUTO2 (50 / 60 Hz MODE) 60 Hz mode 262H forced 312H forced AFC-Gain Normal Normal Free run Free run Normal Normal Free run Free run V pull-in range 224.5H~353H 224.5H~297H 32.5H~353H 32.5H~297H (100000) CENTER Normal OFF (000) AUTO1 POWER-ON INITIAL VALUE
Adjusts B-Y / R-Y black level ; -68 mV~+68 mV Switches gate pulse phase ; (0) : Normal , (1) : -200 ns (Ahead) Switches Y output offset ; +10 IRE : ON / OFF (0) : OFF, (1) : ON Switches SW output mode. Switches YUV / RGB (matrix coefficient) output. (00) : Y / U / V, (01) : RGB / PAL, (10) : RGB / NTSC1, (11) : RGB / NTSC2
OUTPUT MODE
(00) Y/U/V
HD-PHS
(0) : PHASE-1 (1) : PHASE-2 (SCP)
Read function
PARAMETER PORSET COLOR SYSTEM X'tal V-FREQ V-STD H-LOCK N-DET Y2-IN, U2 / V2-IN DESCRIPTION Power-on reset. (0) : RESISTER PRESET, (1) NORMAL Color system. Received system (ID, no ID) (00) : B / W, (01) : SECAM, (10) : PAL, (11) : NTSC X'tal mode (00) : -, (01) : 4.43 (N), (10) : M, (11) : 3.58 Vertical frequency ; (0) : 50 Hz, (1) : 60 Hz Decides vertical standard ; (0) : STANDARD, (1) : NON-STANDARD Decides horizontal lock ; (0) : LOCK, (1) : UN-LOCK Decides noise level ; (0) : Low, (1) : High Outputs self diagnosis result. ; (0) : NG, (1) : OK
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I C BUS COMMUNICATION AND RECEPTION METHODS
Slave address : Slave addresses can be changed using the pin 23 voltage.
2
24H (Pin 23-GND)
A6 0 A5 0 A4 1 A3 0 A2 0 A1 1 A0 0 W/R 0/1
2CH (Pin 23-VCC)
A6 0 A5 0 A4 1 A3 0 A2 1 A1 1 A0 0 W/R 0/1
Start and end conditions
Bit transmission
Acknowledgment
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Data transmit format 1
Data transmit format 2
Data receive format
At data reception, the master transmitter changes to the receiver immediately after the first acknowledgment and the slave receiver changes to the transmitter. The end condition is always generated by the master. (* important ) The data read from THIS IC should always be completed in whole two words, not one word, otherwise the IICBUS may cause error.
Option data transmit format
This transmission method automatically increments sub addresses starting from the specified sub address and sets data.
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I2C BUS Conditions
Characteristics Low level input voltage High level input voltage Low level output voltage at 3 mA sink current Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Symbol VIL VIH VOL1 Ii Ci fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Min 0 3.0 0 -10 0 4.0 4.7 4.0 4.7 350 250 4.0 4.7 Typ. Max 1.5 Vcc 0.4 10 10 100 Unit V V V A pF kHz s s s s ns ns s s
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MAXIMUM RATINGS (Ta = 25C)
CHARACTERISTIC Supply Voltage Input Pin Voltage Power Dissipation Power Dissipation Reduction Rate Operating Temperature Storage Temperature SYMBOL VCCmax Vin PD (Note 1) 1 / ja Topr Tstg RATING 12 GND - 0.3 to VCC + 0.3 844 6.75 -20~65 -55~150 UNIT V V mW mW / C C C
Note 1: See figure below. Note 2: Since the device is susceptible to surge, handle with care. Note 3: This IC is not proof enough against a strong E-M field by CRT which may cause function errors and / or poor characteristics. Keeping the distance from CRT to the IC longer than 20 cm, or if cannot, placing shield metal over the IC, is recommended in an application.
Fig. Power dissipation temperature reduction curve
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OPERATING CONDITION
CHARACTERISTIC Supply Voltage Pin 40 Y Input Signal Level Pin 6 Chroma Input Signal Level Pin 8 Sync Signal Input level Pin 9 Sink Current Pins 18, 19 Pins 41, 42 White 100%. Including sync signal TOF : OFF, burst level TOF : ON, burst level White 100%. Including sync signal CONDITION MIN 8.5 4.7 0.9 200 100 0.9 TYP. 9.0 5.0 1.0 300 200 1.0 0.5 MAX 9.5 5.3 1.1 400 300 1.1 1.0 UNIT V Vp-p mVp-p Vp-p mA
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, Ta = 25C 3C) Current dissipation
PIN No. 18 19 41 42 PIN NAME SYNC VCC SW VCC DAC VCC C VCC SYMBOL ICC1 ICC2 ICC3 ICC4 TEST CIRCUIT MIN TYP. MAX UNIT
13
19
25 mA
24
35
46
PIN VOLTAGE
PIN No. 1 2 3 6 7 12 20 21 22 25 26 27 29 30 31 37 40 PIN NAME 4.43 MHz X'tal N-X'tal 3.58 MHz X'tal C input V-SEP 32 fH VCO Y / G output B-Y / B output R-Y / R output Y2 input B-Y2 input R-Y2 input Y1 input B-Y1 input R-Y1 input Y output Y input SYMBOL V1 V2 V3 V6 V7 V12 V20 V21 V22 V25 V26 V27 V29 V30 V31 V37 V40 TEST CIRCUIT MIN 3.60 3.60 3.60 1.30 5.10 5.30 3.90 3.90 3.90 5.30 5.30 5.30 5.30 5.30 5.30 1.60 2.10 TYP. 4.00 4.00 4.00 1.75 5.50 5.70 4.30 4.30 4.30 5.70 5.70 5.70 5.70 5.70 5.70 2.00 2.50 MAX 4.40 4.40 4.40 2.20 5.90 6.10 4.70 4.70 4.70 6.10 6.10 6.10 6.10 6.10 6.10 2.40 2.90 V UNIT
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AC CHARACTERISTICS
Video block
CHARACTERISTIC Y Input Clamp Voltage Y Input to Y Output AC Gain Y Input to Y Output Frequency Bandwidth TRAP Filter Characteristic Y Input Dynamic Range Y Input to Y Output Transmission Characteristic 1 SYMBOL VYI GYs GYt GfY GTC3 GTC4 VD TYa TYb TY3 Y Input to Y Output Transmission Characteristic 2 TY4 TYS VSU+
Sub Contrast Range VSU- Y Output Offset Amount VYO
TEST CIRCUIT -3 dB
TEST CONDITION Y input-AC GND (Note V1)
MIN 2.1 -0.13 -0.13 8 1.3 255 335 255 255 445
2.5 -3.5 60
TYP. 2.4 0 0 10 -25 -25 1.6 295 375 295 295 495
3.0 -3.0 95
MAX 2.8 0.13 0.13 -13 -13 335 415 335 335 535
3.5
UNIT V
dB
fO = 3.579545 MHz fO = 4.433619 MHz Sub contrast : min. Black and white, Y-DL : OFF Black and white, Y-DL : ON 3.58 NTSC, Y-DL : OFF 4.43 PAL, Y-DL : OFF SECAM, Y-DL : OFF 20 log (Data max. / data center)
20 log (Data max. / data center) (Note V2)
Vp-p
ns
dB -2.5 130 mV
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Chroma block
CHARACTERISTIC SYMBOL F600 F300 ACC Characteristics F30 F10 A Sub Color Control Characteristic es+ es- 3 APC Frequency Control Sensitivity 4 M f3ph f3pl APC Pull-In Range f4ph f4pl fMph fMpl f3hh f3hl APC Hold Range f4hh f4hl fMhh fMhl fO3 fsc Free-Run Frequency fO4 fOM f3c fsc Output Amplitude f4c fMc fsc Output DC Level V44a V44b vRNUV vBNUV Color Difference Output Level vRNCbCr vBNCbCr vRP vBP vR / BUV Relative Amplitude vR / BCbCr vR / BPAL TEST CIRCUIT At 3.58 NTSC, upper side At 3.58 NTSC, lower side At 4.43 PAL, upper side At 4.43 PAL, lower side At M-PAL, upper side At M-PAL, lower side At 3.58 NTSC, upper side At 3.58 NTSC, lower side At 4.43 PAL, upper side At 4.43 PAL, lower side At M-PAL, upper side At M-PAL, lower side fO = 3.579545 MHz fO = 4.433619 MHz fO = 3.575611 MHz At 3.58 NTSC input At 4.43 PAL input At M-PAL input At 3.58 NTSC input At other than 3.58 NTSC input 3.58 NTSC - UV mode, B:C=1:1 3.58 N-CbCr mode, B:C=1:1 4.43 PAL, B:C=1:1 3.58 NTSC - UV mode 3.58 N - CbCr mode 4.43 PAL (Note C2) 20 log (Data max. / data center) 20 log (Data max. / data center) (Note C1) TEST CONDITION MIN 300 300 300 170 0.95 2.0 -7.4 0.5 0.5 0.5 250 -2000 250 -2000 250 -2000 250 -2000 250 -2000 250 -2000 -200 -200 -200 0.45 0.50 0.45 2.9 1.15 300 280 215 280 315 315 0.94 0.94 0.94 TYP. 360 360 360 245 1.00 3.0 -5.3 1.65 1.65 1.65 600 -1400 600 -950 600 -1100 600 -1400 600 -950 600 -1100 0 0 0 0.75 0.65 0.75 3.2 1.55 360 340 272 340 380 380 1.00 1.00 1.00 MAX 420 420 420 290 1.05 4.0 dB -2.4 2.2 2.2 2.2 2000 -250 2000 -250 2000 -250 2000 -250 2000 -250 2000 -250 200 200 200 0.95 0.80 0.95 3.5 1.75 420 400 320 400 440 440 1.15 1.15 1.15 mVp-p V Vp-p Hz Hz / mV mVp-p UNIT
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CHARACTERISTIC SYMBOL BNUV RNUV Demodulation Angle BNCbCr RNCbCr BP RP UVMAX Color Difference Output Tint Adjustment Characteristic UVMIN CbCrMAX CbCrMIN Residual Carrier Level Residual Harmonic Level 1HDL CONT Output DC Level Change ve vHe VDLP VDLS VDLN SCH Sand Castle Pulse Wave High Value SCM SCL SEN SECAM ID Output DC Level SEP SES vNCL NTSC Ident Sensitivity vNCH vNBL vNBH vPCL PAL Ident Sensitivity vPCH vPBL vPBH GFH3 GFC3 TOF Characteristic GFL3 GFH4 GFC4 GFL4 TEST CIRCUIT (Note C6) (Note C5) (Note C4) (Note C3) TEST CONDITION 3.58 NTSC - UV mode, TINT ; center 3.58 N-CbCr mode, TINT ; center 4.43 PAL UV Mode, TINT ; max. UV Mode, TINT ; min. CbCr Mode, TINT ; max. CbCr Mode, TINT ; min. fsc level (fsc x 2) level PAL signal input SECAM signal input NTSC signal input CP level HP level VP level MIN 0 90 0 90 -3.0 87 29 -35 29 -35 4.0 2.2 0 7.6 4.05 2.25 3.4 3.4 0.4 2.0 0.5 1.7 0.3 1.5 1.0 1.5 1.0 14.0 12.5 10.5 15.5 14.0 12.0 TYP. 3 93 3 93 0 90 32 -32 32 -32 1.9 1.9 4.3 2.5 0.1 7.9 4.3 2.5 3.7 3.7 0.7 2.9 1.8 2.7 1.6 4.5 2.8 4.1 2.5 16.5 15.0 13.0 18.0 16.5 14.5 MAX 8 96 8 96 5.5 95 35 -29 35 -29 4.0 4.0 4.6 2.8 0.2 8.2 4.55 2.75 4.0 4.0 1.0 4.0 4.0 5.8 3.6 6.5 3.1 6.1 4.5 19.0 17.5 15.5 20.5 19.0 17.0 dB mVp-p V mVp-p UNIT
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Switch block
CHARACTERISTIC SYMBOL GY1 GY2 GBY1 Color Difference Gain (Through Mode) GRY1 GBY2 GRY2 GY1GP GY1GN1 GY1GN2 GY1BP Y Gain (Matrix Mode) GY1BN1 GY1BN2 GY1RP GY1RN1 GY1RN2 GGYP GGYN1 GGYN2 GBYP Color Difference Gain (Matrix Mode) GBYN1 GBYN2 GRYP GRYN1 GRNY2 RP R-Y Relative Phase RN1 RN2 vPR / B R-Y Relative Amplitude vN1R / B vN2R / B GP G-Y Relative Phase GN1 GN2 vPG / B G-Y Relative Amplitude vN1G / B vN2G / B TEST CIRCUIT RGB / PAL Mode RGB / NTSC1 Mode RGB / NTSC2 Mode RGB / PAL Mode RGB / NTSC1 Mode RGB / NTSC2 Mode RGB / PAL Mode RGB / NTSC1 Mode RGB / NTSC2 Mode RGB / PAL Mode RGB / NTSC1 Mode RGB / NTSC2 Mode (Note S4) (Note S3) (Note S2) TEST CONDITION MIN -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -1.0 -0.6 -0.6 -1.0 8.9 7.5 7.5 3.9 5.6 4.2 87 89 93 0.53 0.77 0.65 234 237 237 0.31 0.37 0.34 TYP. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0.6 0.6 0 9.9 8.5 8.5 4.9 6.6 5.2 90 92 96 0.56 0.80 0.68 237 240 240 0.34 0.40 0.37 MAX 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.6 1.6 1.0 10.9 9.5 9.5 5.9 7.6 6.2 93 95 99 0.59 0.83 0.71 240 243 243 0.37 0.43 0.40 dB UNIT
Y Gain (Through Mode)
(Note S1)
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CHARACTERISTIC SYMBOL VY Switch Output Switch Offset VB VR VYO Switch Output Offset Amount VBO VRO VYB+ Y / G Output Black Level Range VYB- VYO+ VYO- VBB+ B-Y / G Output Black Level Range VBB- VBO+ VBO- VRB+ R-Y / G Output Black Range VRB- VRO+ VRO- VYSM Smoothing Level VBSM SRSM Switch Output Dynamic Range Inter-Input Crosstalk DTH DMT GCR TEST CIRCUIT Through mode Matrix mode Crosstalk between inputs Blanking period voltage (Note S8) (Note S7) (Note S6) (Note S5) TEST CONDITION MIN -85 61 61 59 -82 59 -82 61 -75 61 -75 61 -75 61 -75 4.0 4.0 4.0 1.5 0.9 TYP. 0 0 0 -75 68 68 65 -75 65 -75 68 -68 68 -68 68 -68 68 -68 4.3 4.3 4.3 2.3 1.2 -50 MAX 50 50 50 -65 75 75 71 -68 71 -68 75 -61 75 -61 75 -61 75 -61 4.6 4.6 4.6 -40 Vp-p dB V mV UNIT
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Sync processor block
CHARACTERISTIC 32 fH VCO Oscillation Start Voltage Horizontal Free-Run Frequency Horizontal Oscillation Frequency Range Horizontal Oscillation Frequency Control Sensitivity Horizontal Sync Phase External Pulse Input Threshold (Pin 17) Horizontal Blanking Start Phase Horizontal Blanking Width Gate Pulse Start Phase Gate Pulse Width Horizontal Blanking Pulse Start Phase Horizontal Blanking Pulse Width HD Output Start Phase HD Output Pulse Width HD Amplitude Vertical Blanking Pulse Start Phase Vertical Blanking Pulse Width SYMBOL VVCO f50HO f60HO fHmin fHmax H Sph1 Sph2 CPV17 HPV17 HPs HPw GPs GPw HPs HPw HDs HDw VHD VP50s1 VP60s1 VP50s2 VP60s2 f50vo f60vo Vvh Vvl TEST CIRCUIT AUTO mode (353H) 60 Hz mode (297H) Pin 13 high voltage Pin 13 low voltage (Note D6) (Note D5) Clamp pulse Horizontal blanking (Note D2) TEST CONDITION Pin 18 voltage AUTO mode 60 Hz mode Pin 10 ; 10 k-VCC Pin 10 ; 10 k-GND (Note D1) MIN 3.7 15.455 15.564 14.700 16.500 2.3 0.30 0.11 3.2 0.7 4.1 11.0 2.8 1.8 3.8 9.5 -0.2 1.6 4.7 46 46 40 48 4.7 TYP. 4.0 15.625 15.734 15.000 16.700 2.8 0.40 0.21 3.5 1.0 4.4 11.5 3.0 2.0 4.0 10.0 0 1.8 5.0 48 48 23 21 45 53 5.0 0 MAX 4.3 15.795 15.904 15.300 16.900 3.3 0.50 0.31 3.8 1.3 4.7 12.0 3.2 2.2 4.2 10.5 0.2 2.0 5.3 50 50 50 58 5.3 0.3 V s s s kHz / V s kHz UNIT V
V
(Note D3)
(Note D4)
H
Vertical Free-Run Frequency
Hz
Vertical Output Voltage
V
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CHARACTERISTIC SYMBOL Td Tw fPL1 fPH1 fPL2 fPH2 fPL3 fPH3 fPL4 fPH4 Vadd TEST CIRCUIT Pin 23 voltage (Note D8) TEST CONDITION (Note D7) MIN 42 0.5 TYP. 44 8 224.5 353 32.5 353 224.5 297 32.5 297 0.65 MAX 46 0.8 V H UNIT s
Vertical Output Pulse Width
Vertical Pull-In Range (1)
Vertical Pull-In Range (2)
Vertical Pull-In Range (3)
Vertical Pull-In Range (4) Address Switch Threshold Value
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TEST METHODS (Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25C 3C)
Video block
NOTE CHARACTERISTIC 00 TEST CONDITION SUB ADDRESS & DATA SW MODE 01 02 03 05 SW1 SW2 SW12 TEST METHOD (1) Input signal 2 to Y input (Pin 40) and Yin2 input. (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) V1 Y Input to Y Output AC Gain 80 80 80 or 84 80 80 B A A (2) Change the sub address (02) data to TRAP-OFF (80h) and TRAP-ON (84h) and perform the following : (3) Measure the picture period amplitude (v37) of the Y output (Pin 37) and determine the gain from Y input. GYs, GYt = 20 log (v37 / 0.2) (GYs ; TRAP-OFF, GYt ; TRAP-ON) (1) Input signal 2 to Y input (Pin 40) and Yin2 input. (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) V2 Y Output Offset Amount 80 0 80 80 80 or 81 B A A (2) Set the sub address (01) data to 00 and measure the minimum potential (VYO1) of the Y output (Pin 37) picture period amplitude. (3) Set the sub address (05) data to Y-OFST-ON (81), measure the minimum potential (VYO2) of the Y output picture period amplitude, and determine the difference from VYO1. VYO = VYO2 - VYO1
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TA1270BFG
Chroma block
NOTE CHARACTERISTIC 00 TEST CONDITION SUB ADDRESS & DATA SW MODE 01 02 03 05 SW1 TEST METHOD (1) Input 3.58-NTSC signal 1 rainbow signal (Burst : chroma = 1 : 1) to the chroma input (Pin 6). C1 ACC Characteristics 80 80 80 80 80 B (2) Measure the amplitude, F10, F30, F300, and F600, of the B-Y output (Pin 47) when the amplitude of the chroma input signal is set to 10, 30, 300, and 600 mVp-p. (3) Calculate A = F30 / F300. (1) Connect the chroma input pin (Pin 6) to GND via a capacitor. 80 C2 APC Frequency Control Sensitivity 80 80 81 or 83 or 84 80 or 81 B (2) Change the sub address (03) data to (81h), (83h), and (84h) and perform the following for each. (3) Connect external power source (V4) to the APC filter (Pin 4). (4) Vary the voltage of external power source (V4) and measure the Fsc output (Pin 44) using a frequency counter. (5) Measure the free-run sensitivity for the (V4 + 100 mV) near fsc. (3.58NTSC ; 3, 4.43 ; PAL ; 4 ; M-PAL ; M) 80 C3 SECAM ID Output DC Level 80 80 81 or 83 or 84 80 B (1) Connect the chroma input pin (Pin 6) to GND via a capacitor. (2) Change the sub address (03) data to (81h), (83h), and (84h) and measure the output DC level of the SECAM ID (Pin 46). 3.58 NTSC mode (81h) ; SEN 4.43 PAL mode (83h) ; SEP SECAM mode (84h) ; SES (1) Input 3.58-NTSC signal 1 rainbow signal (Burst : chroma = 1 : 1) to the chroma input (Pin 6). 80 C4 NTSC Ident Sensitivity 80 or 81 80 80 80 A (2) While monitoring READ BUS "COLOR", perform the following with BUS "P / N-ID" data = 1 and 0. (3) Increase the amplitude of the input signal from 0 mVp-p and measure the amplitude at mode change to 3.58 NTSC mode.(Normal (1) ; vNCL, High (0) ; vNCH) (4) Decrease the amplitude of the input signal from 100 mVp-p and measure the amplitude at mode change to 3.58 NTSC mode. (Normal (1) ; vNBL, High (0) ; vNBH)
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TA1270BFG
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25C 3C)
NOTE CHARACTERISTIC 00 TEST CONDITION SUB ADDRESS & DATA SW MODE 01 02 03 05 SW1 TEST METHOD (1) Input 4.43 PAL signal 1 rainbow signal (Burst : chroma = 1 : 1) to the CHROMA input (Pin 6). 80 C5 PAL Ident Sensitivity 80 or 81 80 80 80 A (2) While monitoring the READ BUS "COLOR", perform the following with BUS "P / N-ID" data = 1 and 0. (3) Increase the amplitude of the input signal from 0 mVp-p and measure the amplitude at mode change to 4.43 PAL mode. (Normal (1) ; vPCL, High (0) ; vPCH) (4) Decrease the amplitude of the input signal from 100 mVp-p and measure the amplitude at mode change to 4.43 PAL mode. (Normal (1) ; vPBL, High (0) ; vPBH) (1) Input fsc signal to the chroma input (Pin 6).(signal amplitude = 10 mVp-p, f01 = 3.579545 MHz,f02 = 4.433619 MHz) (2) Set sub address (01) data to (38h). With f01, set sub address (03) data to (81h) ; with f01, to (83h). Insert a 1.5 k resistor between R-Y output (Pin 48) and VCC (5 V). Monitor R-Y output (Pin 48) and perform the following. (3) Measure the output amplitude with f0 and calculate the gain from the input. (f01 ; GFC3, f02 ; GFC4) (4) Measure the output amplitude with f0 500 kHz and calculate the gain from the input. (f01 + 500 kHz ; GFH3, f01 - 500 kHz ; GFL3, f02 + 500 kHz ; GFH4, f02 - 500 kHz ; GFL4)
80 C6 TOF Characteristics
83
80
81 or 83
80
A
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TA1270BFG
Switching block (Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25C 3C)
NOTE CHARACTERISTIC TEST CONDITION SUB ADDRESS & DATA SW MODE 00 01 02 SW2 A Y Gain (Through Mode) SW6 B or A SW11 SW8 SW9 A or B SW16 TEST METHOD (1) Input signal 2 to Yin2 input. (f0 = 100 kHz, picture period amplitude = 0.2 Vp-p) (2) Apply DC = 5 V to Ys input (Pin 32). (3) Input signal 2 to Y1 input (Pin 29). (4) Measure the output amplitude of Y / G output (Pin 20) and calculate the gain from the input. (5) Input signal 2 to Y2 input (Pin 25), set Ys input (Pin 32) DC = 0 V, and repeat (3) and (4) above. (Y1~Y / G ; GY1, Y2~Y / G ; GY2) (1) Same as (1) and (2) for S1 above. (2) Input signal 2 to B-Y1 input (Pin 30) and input +90 phase signal of signal 2 to R-Y1 input (Pin 30). (3) Measure the amplitude of the B-Y / B output and the R-Y / R output and calculate the gain from the input. (4) Input signal 2 to B-Y2 input (Pin 26) and input +90 phase signal of signal 2 to the R-Y2 input (Pin 27). (5) Set the Ys input pin DC = 0 V and repeat (4) above. (B-Y1~B-Y / B ; GBY1, R-Y1~R-Y / R ; GRY1 B-Y2~B-Y / B ; GBY2, R-Y2~R-Y / R ; GRY2) SW8 SW9 A or B SW16 (1) Same as (1) and (2) for S1 above. (2) Change the sub address (06) data to PAL (81h), NTSC1 (82h), and NTSC2 (83h), perform the following. (3) Input signal 2 to Y1 input (Pin 29), measure the amplitude of Y / G output, B-Y / B output, R-Y / R output, and calculate the gain from the input. (Y1~Y / G : PAL ; GY1GP, NTSC1 ; GY1GN1, NTSC2 ; GY1GN2 Y1~B-Y / B : PAL ; GY1BP, NTSC1 ; GY1BN1, NTSC2 ; GY1BN2 Y1~R-Y / B : PAL ; GY1RP, NTSC1 ; GY1RN1, NTSC2 ; GY1RN2)
S1
80
80
80
SW10
SW14
B
B
A
SW2 80 80 81 or 82 or 83 A
SW6 A or B SW11 A or B
SW8 B or A SW14 A
SW9 B or A SW16
S2
Color Difference Gain (Through Mode)
SW10 A or B
SW2 80 S3 Y Gain (Matrix Mode) 80 81 or 82 or 83 A
SW6 B or A SW11 B
SW10 B
SW14 A
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TA1270BFG
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25C 3C)
NOTE CHARACTERISTIC TEST CONDITION SUB ADDRESS & DATA SW MODE 00 01 02 SW2 80 S4 Color Difference Gain (Matrix Mode) 83 81 or 82 or 83 A SW6 A or B SW11 A or B SW6 B SW6 B SW6 B SW6 B SW8 B or A SW14 A SW9 B or A SW16 TEST METHOD (1) Same as (1) and (2) for S2 above. (2) Change the sub address (05) data to PAL (81h), NTSC1 (82h), and NTSC2 (83h), perform the following. (3) Measure the amplitude of Y / G output, B-Y / B output, R-Y / R output, then calculate the gain from the input. (Y1~Y / G : PAL ; GGYP, NTSC1 ; GGYN1, NTSC2 ; GGYN2 Y1~B-Y / B : PAL ; GBYP, NTSC1 ; GBYN1, NTSC2 ; GBYN2 Y1~R-Y / R : PAL ; GRYP, NTSC1 ; GRYN1, NTSC2 ; GRYN2) (1) Input signal 2 to Yin2. (2) Apply DC = 5 V to Ys input (Pin 32). (3) Change the sub address (04) data from (80h) to (88h) and measure DC variation VYO, VBO, and VRO of Y / G output, B-Y / B output, and R-Y / R output picture period. (1) Same as (1) and (2) for S1 above. (2) Change the sub address (04) data from (80h) to (F0h) and measure the DC variation VYB+ of the Y / G output (Pin 20) picture period. Also change the data from (80h) to (00h) and measure the DC variation VYB-. (3) Change the sub address (04) data from (88h) to (F8h) and from (88h) to (08h), then measure VYO+ and VYO-. (1) Same as (1) and (2) for S1 above. (2) Change the sub address (06) data from (80h) to (00h) and measure the DC variation VBB+ of the B-Y / B output (Pin 21) picture period. Also change the data from (80h) to (F8h) and measure the DC variation VBB-. (3) Change the sub address (04) data to (88h) and measure VBO+ and VBO- same as (2) above. (1) Same as (1) and (2) for S1 above. (2) Change the sub address (05) data from (80h) to (00h) and measure the DC variation VRB+ of the R-Y / R output (Pin 22) picture period. Also change the data from (80h) to (F8h) and measure the DC variation VRB-. (3) Change the sub address (04) data to (88h) and measure VRO+ and VRO- same as (2) above.
SW10 A or B SW2 A SW14 A SW2
SW7 B SW7 B SW7 B SW7 B
SW8 B SW8 B SW8 B SW8 B
S5
Switch Output Offset Amount
80
80
80
S6
Y / G Output Black Level Range
Variable
80
80
A SW14 A SW2
S7
B-Y / B Output Black Level Range
80
80
Variable
A SW14 A SW2
S8
R-Y / R Output Black Level Range
80
Variable
80
A SW14 A
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TA1270BFG
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25C 3C)
TEST CONDITION NOTE CHARACTERISTIC SW2 A D1 Horizontal Sync Phase SW MODE SW4 SW5 B A TP32 5V TEST METHOD (1) Input signal in the figure below from TG7 to Y2in. (2) Measure the pin 10 waveform phase difference Sph1 in relation to the TP8 waveform. (3) Set the sub address (05) D1 as 1 and measure Sph2 same as (1) above. Horizontal Blanking Start Phase D2 Horizontal Blanking Pulse Width Gate Pulse Start Phase D3 Gate Pulse Width D4 Horizontal Blanking Pulse Start Phase Horizontal Blanking Pulse Width HD Output Start Phase D5 HD Output Pulse Width HD Output Amplitude Vertical Blanking Pulse Start Phase D6 Vertical Blanking Pulse Width A D7 Vertical Pulse Width B A 5V A B A 5V A B A 5V A B A 5V A B A 5V A B A 5V (1) Same as (1) for D1. (2) Measure phase differences HPs and HPw for pin 10 and pin 21, respectively (1) Same as (1) for D1. (2) Measure the pin 15 waveform phase difference GPs in relation to the pin 10 waveform and measure pulse width GPw. (1) Same as (1) for D1. (2) Measure HPs and HPw same as (2) for D3. (1) Same as (1) for D1. (2) Measure the pin 14 waveform phase difference HDs in relation to the pin 10 waveform and measure pulse width HDw and amplitude VHD. (1) Input 50Hz CVBS signal to Y2in. (2) Measure the pin 15 waveform phase difference VP50s1 in relation to the pin 8 waveform and measure pulse width VP50s2. (3) Input 60Hz CVBS signal to Y2Yin. (4) Measure VP60s1 and VP60s2 same as (2) above. (1) Input 60Hz CVBS signal to Y2in. (2) Measure the delay Td of the pin 13 vertical pulse in relation to the pin 8 vertical signal and measure the pulse width Tw.
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TA1270BFG
(Unless otherwise specified, SYNC / SW VCC = 9 V, DAC / C VCC = 5 V, preset bus data, Ta = 25C 3C)
TEST CONDITION NOTE CHARACTERISTIC SW2 A Vertical Pull-In Range (1) SW MODE SW4 SW5 B A TP32 5V TEST METHOD (1) Input 50 Hz CVBS signal to Y2in. (2) Change the input signal vertical frequency in 0.5 H steps and measure the pull-in ranges fPL1 and fPH1. (3) Set the sub address (04) D2 / D1 / D0 to (100) and measure fPL2 and fPH2 same as in (2). (4) Input 60 Hz CVBS signal to Y2in and set the sub address (04) D2 / D1 / D0 to (001). (5) Change the input signal vertical frequency in 0.5 H steps and measure the pull-in ranges fPL3 and fPH3. Vertical Pull-In Range (4) (6) Set the sub address (04) D2 / D1 / D0 to (101) and measure fPL4 and fPH4 same as (5).
Vertical Pull-In Range (2) D8 Vertical Pull-In Range (3)
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TA1270BFG
TEST SIGNALS
1) Signal 1 (Rainbow signal)
2)
Signal 2
3)
Signal 3
4)
Signal 4
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TA1270BFG
(Note D6)
VERTICAL BLANKING PULSE
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TA1270BFG
(Note D6)
VERTICAL OUTPUT PULSE WIDTH
33
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TA1270BFG
TEST CIRCUIT
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TA1270BFG
APPLICATION CIRCUIT 1 (NTSC)
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TA1270BFG
APPLICATION CIRCUIT 2 (MULTI)
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TA1270BFG
APPLICATION CIRCUIT 3 (South America)
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TA1270BFG
PACKAGE DIMENSIONS
QFP48-P-1014-0.80 Unit: mm
Weight: 0.83g (Typ.)
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TA1270BFG
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2005-08-18

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